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SST flash fix

The reason why the SST flash doesn't work correctly in the DTV is that the chip sees every write cycle two times instead of one.

If you look at the capture from my logicanalyzer, you will see that there are two low pulses on the /WR line for the write access. For some reason I don't know, every write access of the DTV looks like this.
The green column is where the logicanalyzer triggered on the signal (and /CS goes low at the same instant. My logicanalyzer and the Atmel flash don't see this as a triggerpoint, but it seems that the SST Flash sees a second write pulse here. That of course breaks the magic sequences needed to write to the flash.

Fortunately there is a simple hardware-fix for the problem: when one just adds a 47pF capacitor from the /CS line of the flash to GND (or VCC), the /CS pulse is slightly delayed, and the first /WR pulse isn't seen as a write access anymore.

Control signals during a flash write access
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Capacitor fix added
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